This invention relates to circuits for compressing a digital image such that the compressed image retains its fidelity.
By a digital image is herein meant an array of pixels which are arranged in rows and columns. Such an array is called a frame; and, it is generated by various video sources like, for example, a digital camera or a digital storage device which stores and regenerates the camera images.
Each pixel consists of a certain number of bits which specify the brightness of the image at the pixel's row-column location in the frame. A pixel having "X" bits will range in magnitude from 0 to 2.sup.x -1. A magnitude of 0 corresponds to minimum brightness; a magnitude of 2.sup.x -1 corresponds to maximum brightness; and the remaining magnitudes between 0 and 2.sup.x -1 correspond to intermediate brightness levels.
Suppose now that a digital image having X bits per pixel is to be displayed on a video display which can accommodate only Y-bits per pixel, where Y is less than X. For example, suppose the video source provides an image with 5-bits per pixel (32 brightness levels), but the video display can only display pixels with 3-bits (8 brightness levels).
In the above case, the 5-bit pixels must somehow be compressed to 3-bit pixels. However, in making that compression it would seem that a loss of fidelity in the displayed image is unavoidable. Such a loss of fidelity will occur if, for example, the 3-bit pixel is obtained by simply stripping off the two least significant bits from the 5-bit pixel.
Accordingly, a primary object of the invention is to provide an image compressing circuit which compresses X-bit pixels to Y-bit pixels, where Y is less than X, while retaining image fidelity.